Architecture, Compilers, and Parallel Computing

a supercomputer installationAs we approach the end of Moore’s Law, and as mobile devices and cloud computing become pervasive, all aspects of system design—circuits, processors, memory, compilers, programming environments—must become more energy efficient, resilient, and programmable.

Our research groups explore energy efficiency via low-voltage design techniques, specialized hardware accelerators, adaptive runtime techniques in high performance computing, efficient memory architectures for heterogeneous mobile systems, novel architectures for exascale systems, and other projects. We examine resilience through tolerating variation during chip fabrication, failure-tolerant processor architectures, scalable resilience protocols, and automated software debugging and recovery techniques. We explore programmability through architectural support for synchronization, automatic parallelization and vectorization, performance-portability for heterogeneous mobile systems, high-performance implementations of scripting languages, and highly scalable parallel run-time systems.

In addition to collaborating with major companies, our software artifacts like LLVM and Charm++ are widely used in industry, government labs, and academic research.

CS Faculty and Their Research Interests

Sarita Adve parallel computing, memory architecture, power- and reliability-aware architectures 
Vikram Adve compiler infrastructures and techniques, secure architectures, heterogeneous systems 
Maria J. Garzaran compilers, hardware-software interaction, software frameworks for high-performance computing 
William Gropp programming models and systems for parallel computing 
Laxmikant Kale large-scale parallel systems; runtime systems, tools, and frameworks for high-performance computing 
David Padua compiler techniques for parallel computing 
Rob A. Rutenbar accelerator architecture, approximate computing, FPGA, VLSI, CAD 
Marc Snir large-scale parallel systems, algorithms, and libraries 
Josep Torrellas parallel architectures, power- and reliability-aware hardware/software architectures 
Craig Zilles compilers, dynamic optimization, computer science education 

Affiliate Faculty

Deming Chen, Electrical & Computer Engineering hardware/software co-design for system-on-chip; reconfigurable computing; GPU computing and optimization
Wen-mei Hwu, Electrical & Computer Engineering HPC and parallel systems, compilers, GPU programming
Nam Sung Kim, Electrical & Computer Engineering non-conventional computer architecture: bio-inspired, molecular, cellular, and analog-digital hybrid computing 
Rakesh Kumar, Electrical & Computer Engineering power- and reliability-aware architectures, approximate computing 
Steve Lumetta, Electrical & Computer Engineering parallel computing, architecture, reliability, architectures for genomic applications 
Sanjay Patel, Electrical & Computer Engineering high-performance and parallel systems
Shobha Vasudevan, Electrical & Computer Engineering system verification and security; analog and digital hardware validation 
Martin Wong, Electrical & Computer Engineering computer-aided design of integrated circuits

Architecture, Compilers, and Parallel Computing Research Efforts and Groups

Architecture, Compilers, and Parallel Computing News

CS Professor William D. Gropp

CS professor helps chart NSF’s future advanced computing strategy and programs

July 6, 2016   CS Professor Bill Gropp co-chaired a National Academies study that guides the NSF’s future directions in advanced computing.
CS Professor Josep Torrellas

NSF funds research to advance scalability for on-chip wireless communications

July 5, 2016   CS researchers to receive $880,000 in NSF funding to to advance scalability for on-chip wireless communications.
Josep Torrellas

Torrellas Elected to CRA Board of Directors

March 8, 2016   Josep Torrellas has been elected to the Computing Research Association (CRA) Board of Directors.
Josep Torrellas

Torrellas Receives Funding for Phase 2 of a DARPA PERFECT Project

April 24, 2014   Josep Torrellas has been awarded for funding Phase 2 of a DARPA-funded project.
William Gropp investiture

Gropp Invested as First Thomas M. Siebel Chair in Computer Science

April 22, 2014   On April 3,William D. Gropp was invested as the first Thomas M. Siebel Chair in Computer Science.